A Beginner's
Guide to FPGA

01What is an FPGA?

A normal processor (CPU) has fixed hardware. You can't change the transistors — you can only feed it different software. An FPGA is the opposite: it's a sea of generic logic blocks and wires that you configure into whatever digital circuit you want. Want a 16-bit adder? A video decoder? A custom CPU of your own design? You describe the circuit, load it onto the FPGA, and the chip physically becomes that circuit.

"Field-programmable" means you reconfigure it after manufacturing — at your desk, as many times as you like. "Gate array" means it's built from a regular grid of logic elements.

02FPGA vs CPU vs GPU vs ASIC

• CPU — fixed silicon, runs software sequentially. Flexible, easy to program, but does one thing at a time per core.
• GPU — thousands of identical cores for the same operation on lots of data. Great for graphics/ML, still fixed hardware.
• FPGA — reconfigurable hardware. True parallelism, deterministic timing (great for real-time signal processing, low-latency I/O), but harder to design and slower clock speeds than a CPU.
• ASIC — a circuit baked permanently into custom silicon. Fastest and cheapest at huge volume, but you can never change it and it costs a fortune to make. FPGAs are often used to prototype ASICs.

03What's inside the chip

You don't wire up individual transistors. An FPGA gives you a few repeating building blocks:

• LUTs (Look-Up Tables) — tiny memories that implement any logic function of a few inputs. These are the fundamental gates of the FPGA world.
• Flip-flops — 1-bit memory cells that hold state between clock ticks. LUT + flip-flop together = a "logic cell" (Xilinx calls a cluster a CLB, Intel/Altera an ALM).
• Routing fabric — the programmable wires and switches that connect everything. Most of the chip is actually routing.
• Block RAM (BRAM) — chunks of on-chip memory for buffers and FIFOs.
• DSP slices — hardened multiply-accumulate units for fast math.
• I/O blocks & clock management (PLLs) — drive pins and generate/clean clock signals.

When you "program" an FPGA you're really setting millions of these little switches — that configuration is called the bitstream.

04How you describe a circuit: HDL

You don't draw schematics (mostly). You write a Hardware Description Language. The two big ones:

• Verilog / SystemVerilog — C-like syntax, very popular, great for beginners.
• VHDL — more verbose and strict, common in Europe and aerospace/defense.

The crucial mindset shift: HDL is not a program that runs top to bottom. It describes hardware that all exists at once. When you write two assignments, they happen simultaneously, not in order. Beginners trip on this constantly — keep reminding yourself you're describing wires and gates, not steps.

05The toolchain — from code to chip

Getting your HDL onto the board goes through a pipeline. The vendor IDE handles most of it with one button, but it helps to know the stages:

1. Write HDL — your Verilog/VHDL design + a constraints file mapping signals to physical pins.
2. Simulate — test the logic on your PC before touching hardware (e.g. with Verilator or the built-in simulator). Catches most bugs cheaply.
3. Synthesis — the tool translates your HDL into a netlist of LUTs, flip-flops and wires.
4. Place & route — it decides which physical logic cells to use and how to wire them, while meeting your timing requirements.
5. Generate bitstream — the final configuration file.
6. Program the FPGA — load the bitstream over USB/JTAG. The chip becomes your circuit instantly.

Tools: AMD/Xilinx use Vivado, Intel/Altera use Quartus, Lattice use Radiant/Diamond. There's also a fully open-source flow — Yosys + nextpnr — which is fantastic for hobbyists and works great with Lattice iCE40/ECP5 boards.

06Picking your first board

Don't overbuy. A small, well-documented board with a friendly toolchain beats a powerful one you can't get started on.

• iCEBreaker or TinyFPGA / Icebreaker (iCE40) — cheap, fully open-source toolchain (Yosys/nextpnr). Great hacker choice.
• Digilent Basys 3 / Arty A7 (Xilinx Artix-7) — the classic university board; tons of tutorials, switches, LEDs, displays. Uses Vivado.
• Terasic DE10-Lite / DE0 (Intel MAX 10) — popular in Altera/Quartus courses.
• Tang Nano (Gowin) — very inexpensive, increasingly good open-source support.

07Your first project: blink an LED

"Blinky" is the hello world of hardware. The idea: take the board's clock (say 12 MHz), count its ticks, and toggle an LED every time the counter overflows — giving a visible ~1 Hz blink. In Verilog:

module blink (
    input  wire clk,        // 12 MHz board clock
    output reg  led
);
    reg [23:0] counter = 0; // 24-bit counter

    always @(posedge clk) begin
        counter <= counter + 1;   // increment every clock tick
        if (counter == 0)         // overflowed (~0.7 s at 12 MHz)
            led <= ~led;          // flip the LED
    end
endmodule

You also write a tiny constraints file telling the tool which physical pins clk and led connect to (this is board-specific). Then: synthesize → place & route → bitstream → program. The LED blinks. Congratulations — you just designed hardware.

08Where to go next

• Blink → debounce a button → drive a 7-segment display → UART "hello world" → VGA pattern → a simple state machine.
• Learn timing: clock domains, setup/hold, and why "it works in simulation but not on the board" usually means a timing or constraints problem.
• Build a finite state machine — the backbone of almost every real design.
• Eventually: implement a small soft CPU (e.g. a RISC-V core) — the rite of passage that ties everything together.

Free resources: nandland.com and fpga4fun.com for gentle tutorials, HDLBits for Verilog practice problems, and Digilent's reference docs if you have an Arty/Basys.